b-52 01/99 j174, j175 p-channel silicon junction field-effec t t ransistor choppers commutators analog switches absolute maximum r atings at t a = 25?c reverse gate sou r ce & reverse gate drain v oltage C 30 v continuous fo r ward gate current 50 ma continuous device power dissipatio n 360 mw power derating 3.27 mw/c t oe226aa p ac k age dimensions in inches (mm) pin configu r ation 1 drain, 2 gate, 3 sou r ce surface mount smpj174, SMPJ175 at 25c free air temperature: j174 j175 process pj99 static electrical characteristics min max min max unit t est conditions gate sou r ce breakdown v oltage v (br)gss 30 30 v i g = 1 a, v ds = ? v gate reverse current i gss 1 1 n a v gs = 2 0 v , v ds = ? v gate sou r ce cutoff v oltage v gs(off) 5 1 0 3 6 v v ds = C 1 5 v , i d = C 10 na drain saturation current (pulsed) i dss C 2 0 C 12 5 C 7 C 70 ma v ds = C 1 5 v , v gs = ? v drain cutoff current i d(off) C 1 C 1 n a v ds = C 1 5 v , v gs = 1 0 v dynamic electrical characteristics max max drain sou r ce on resistance r ds(on) 85 85 v gs = ?, v ds < = 0. 1 v f = 1 khz dynamic electrical characteristics t yp t yp drain gate capacitance c gd 5.5 5.5 pf v ds = ? v , v gs = 1 0 v f = 1 mhz sou r ce gate capacitance c gs 5.5 5.5 pf v ds = ? v , v gs = 1 0 v f = 1 mhz drain gate + sou r ce gate capacitance c gd + c gs 32 32 pf v ds = v gs = ? v f = 1 mhz switching characteristics j174 j175 t urn on delay t ime td (on) 2 5 n s v dd C 10 C 6 v rise t ime t r 5 1 0 n s v gs(off) 12 8 v t urn off delay t ime td (off) 5 1 0 n s r l 560 1. 2 k fall t ime t f 10 20 ns v gs(on) ? ? v 1000 n. shiloh road, garland , tx 7 5042 (972) 487-1287 f a x (972) 276-3375 ww w .interfet.com databook.fxp 1/13/99 2:09 pm page b-52
|
